Design Verification Engineer Coop Internship - Fall 2022
Business Line Description:
MCU/MPU Engineering Digital IP team defines and develops components for a wide range of products, including automotive microprocessors, application processors, microcontrollers, and networking. The Austin Digital IP team develops components for DDR, Ethernet, high-speed serial links, cores, caches, interconnect, and other IP
- Defining and writing IP verification plans based on requirements documents (industry standards, product requirements, IP architecture and IP implementation specifications)
- Writing stimulus in System Verilog (UVM), random test scenarios, algorithmic and directed testcases.
- Defining and writing System Verilog Assertion (SVA) cover properties to match the verification plan.
- Writing System Verilog (UVM) monitors, drivers, response checkers and SVAs for correctness.
- Developing and maintaining portions of a verification environment including scripts and Make files.
- Debugging failing testcases to determine source of failure (tool, testcase, checker, verilog RTL) and track resolution
- Collecting code and functional coverage results from random simulations, and analyzing uncovered events to determine additional test scenarios needed to achieve 100% coverage.
- Performing assertion-based formal verification of blocks and IPs to ensure they meet requirements
- Digital IP Functional Verification involves learning precise operating expectations for digital designs containing constant new and innovative features and implementing pre-silicon simulations to test and find and fix every possible bug in the design, in order to achieve the highest level of quality.
- Challenges will include understanding the expected operation of new and innovative features, predicting where bugs are most likely to be hiding in the design, and implementing the most efficient and robust solutions to find and fix design bugs against schedules and deadlines for the products.
- Keen engineering problem solving skills and a mind for seeking innovative solutions to reduce effort while increasing productivity and automation are all areas that are highly valuable in Functional Verification.
Cross functional aspects:
- The design verification engineer will work with other members of the design and verification team to verify IP designed in-house or purchased from 3rd party vendors.
- Minimum candidate for BSEE/BSCE/BSCS. Candidate for MSEE/MSCE/MSCS a plus.
- Programming skills (SystemVerilog, OVM/UVM, Verilog, C/C++, Perl, TCL, etc.) required. UVM is a plus.
- Verilog design skills (Synthesis, static and formal checkers, etc.) are a plus.
NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.